Recent developments in mobile computing and wireless internet have led to an increasing demand for portable computers and smart phones equipped with wireless local area network (WLAN) operating with multi-standard capabilities. More standards and applications will be incorporated in the near future because minimum feature sized transistors in VLSI technology allow more devices on a single chip with massive digital signal processing and memory capabilities. The recently released 2×2 IEEE 802.11ac Wi-Fi technology offers superior performance, while reducing download times and increasing web browsing speed. This technology uses two antennas, but it supports antenna sharing between different standards. The downside is that multiple-input, multiple-output (MIMO) technologies require multiple antennas and multiple transceivers.
Power efficient amplifiers for legacy services and emerging technologies are of primary relevance (S. C. Cripps, “RF Power Amplifiers for Wireless Communications,” Artech House Inc., Norwood Mass., 1999; S. Egolf, “Intelligent Power Management: A Method to Improve 2G/3G Handset Talk Time,” Microwave Journal, pp. 94-100, July 2007; T. Gillenwater, “Evolution of the Smartphone,” Microwave Journal, Vol. 2, February 2017.). Erickson and Heidt (U.S. Pat. No. 4,547,746) suggested that correlating the power supply with output signal power can maintain the power-added efficiency (PAE) by keeping it constant and close to peak value. Power efficient nonlinear amplifiers, such as those found in class AB and B, have been combined to achieve better PAE figures (U.S. Pat. No. 5,175,871).
The envelope tracking technique (class G amplifier) shown in FIG. 1 is useful for improving voltage efficiency. In this case, the power supply is adjusted to the voltage needed for processing the signal. With the evolution of wireless technologies and the demand for multi-standard applications, the aforementioned two techniques were combined by Faulkner and Briffa, as described in U.S. Pat. No. 5,420,536. This technique offers several benefits when large supply voltages are used. However, limited benefits are obtained when low-voltage deep submicron CMOS technologies are employed due to drain-source voltage limitation restrictions. Optimized architectures following this approach are commonly found in recent realizations (U.S. Pat. Nos. 7,042,283, 5,712,593, 5,880,633, 5,880,633, and M. Hassan et al., “High Efficiency Envelope Tracking Power Amplifier with Very Low Quiescent Power for 20 MHz LTE,” IEEE Proc. of the Radio Frequency Integrated Circuits Symposium, June 2011).
Class H architectures employing multiple power supplies to improve power amplifier (PA) power efficiency have also been developed (J. S. Walling et al., “A Class-G Supply Modulator and Class-E PA in 130 nm CMOS,” IEEE J. Solid-State Circuits, pp. 2339-2347, September 2009; S.-M. Yoo, et. al., “A class-G dual-supply switched-capacitor power amplifier in 65 nm CMOS,” in Procc. IEEE RF-IC, June 2012, pp. 233-236; U.S. Pat. No. 8,829,993). The overhead could be excessive, preventing its adoption in massive low-cost consumer electronic products. In other designs, the PA is segmented and coupled to the primary of the transformer, and then the effective load impedance is modulated to efficiently deliver power to the antenna (G. Liu et al., “A 1.2V, 2.4 GHz Fully Integrated Linear CMOS Power Amplifier with Efficiency Enhancement,” Proc. IEEE 2006 Custom Integrated Circuits Conference, pp. 141-144, 2006; I. Aoki et al., “A Fully-Integrated Quad-Band GSM/GPRS CMOS Power Amplifier,” IEEE J. Solid-State Circuits, pp. 2747-2758, December 2008). A different implementation uses a segmented DAC-driven polar PA to implement the envelope tracking technique in current mode (P. T. M. Zeijl and M. Collados, “A Digital Envelope Modulator for a WLAN OFDM Polar Transmitter in 90 nm CMOS,” IEEE J. Solid-State Circuits, pp. 2204-2211, 2007; J. Xiao et al., “A 13-Bit 9GS/s RF DAC-Based Broadband Transmitter in 28 nm CMOS,” Procc. of the IEEE VLSI, pp. C262-C263, September 2013), resulting in a solution that competes with the voltage envelope tracking approach, the main concept of which is shown in FIG. 2. These techniques are especially relevant for polar PAs. The phase is up-converted and fed into the switchable bank of PA sections. The magnitude is used to control the segments of the PA, and thereby modulates the current delivered to the antenna through the impedance matching network. The impedance matching network is used to minimize signal swing within the limits allowed by the CMOS technology (H. Qian et al., “A 35 dBm Output Power and 38 dB Linear Gain PA with 44.9% Peak PAE at 1.9 GHz in 40 nm CMOS,” IEEE Journal of Solid-State Circuits, pp. 587-597, March 2016). The CMOS PA is particularly relevant to emerging technologies because it can take advantage of the powerful signal processors available in this technology (Y. Yoon et al., “A dual-mode CMOS RF power amplifier with integrated tunable matching network,” IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 1, pp. 77-88; A. Afsahi and L. Larson, “Monolithic power-combining techniques for watt-level 2.4-GHz CMOS power amplifiers for WLAN applications,” Transactions on Microwave Theory and Techniques, IEEE Transactions on, vol. 61, no. 3, pp. 1247-1260; A. Niknejad et al., “Design of CMOS power amplifiers,” IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 6, pp. 1784-1796; L. Ye, J Chen et al., “A digitally modulated 2.4 GHz WLAN transmitter with integrated phase path and dynamic load modulation in 65 nm CMOS,” in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International, February 2013, pp. 330-331).
Deep-submicron CMOS technology scaling progress has adverse effects for analog processors, such as lower transistor output impedance, limited voltage headroom, higher flicker noise, and higher hot carrier effects. In addition, process, voltage, and temperature (PVT) variations produce system performance deviations from the desired target. A major limitation in CMOS technology that prevented its adoption in medium and high-power transmitters is its limited efficiency. Therefore, there is still a need for more power efficient CMOS transmitters suitable for wireless applications.